The present invention relates to a semiconductor memory device and, more particularly, to a technique for improving layout of the semiconductor memory device. The invention relates to, for example, a technique which is effectively applied to a static memory in which static memory cells are connected to a plurality of word lines and a plurality of bit lines disposed so as to cross the word lines.
Examples of the semiconductor memory device include a dynamic random access memory (abbreviated as “DRAM”) using dynamic memory cells as memory cells as disclosed in Japanese Unexamined Patent Publication No. 2001-344965 (Patent Document 1) and a static random access memory (abbreviated as “SRAM”) using static memory cells as memory cells as disclosed in Japanese Unexamined Patent Publication No. 2002-368135 (Patent Document 2).
Patent Document 1 describes a technique for reducing parasitic capacitance in data lines in a DRAM. According to the technique, as shown in FIG. 4 of Patent Document 1, a read data line pair is disposed every column of four memory cells, and column selection in data reading operation is performed by four sub read source lines. A write data line pair is disposed every eight memory cells, and column selection in data line writing operation is performed by eight sub write activate lines. By making the number of read data line pairs, the number of write data line pairs, and the number of memory cell columns associated with the read data line pairs and the write data line pairs different from each other, while avoiding conspicuous increase in signal wirings for selecting a column, the wiring pitch of data lines is lessened, and parasitic capacitance is suppressed.